View ADL7003CHIPS-SX_8994551.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

50 ghz to 95 ghz, gaas, phemt, mmic, wideband low noise amplifier data sheet adl7003 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2017 analog devices, inc. all rights reserved. technical support www.analog.com features gain : 14 db typical noise f igure: 5 db typical input return loss (s11) : 15 db typical output return loss (s22) : 20 db typical output power for 1 db compression (p1db) : 1 4 dbm typical saturated output power (p s at ) : 18 dbm typical output third - order i ntercept (ip3) : 21 dbm typical supply v oltage: 3 v at 120 ma 50 ? matched input/output die size: 1.9 mm 1.9 mm 0.05 mm applications test i nstrumentation military and space telecommunications infrastructure functional block dia gram 9 10 11 12 13 14 1 8 7 6 5 4 3 2 v dd 2b v dd 3b v dd 4b v dd 1b v gg 34b v gg 12b rfin rfout adl7003 v dd 4a v dd 3a v gg 34a v dd 2a v dd 1a v gg 12a 15691-001 figure 1 . general description the adl7003 is a gallium arsenide (gaas), pseudomorphic high electron mobility tr ansistor (phemt ), monolithic microwave integrated circuit (mmic), b alanced low noise amplifier that operates from 50 ghz to 95 ghz. in the lower band of 50 ghz to 70 ghz, the adl7003 provides 14 db (typical) of gain, 2 1 dbm output ip3 , and 1 2 dbm of output power for 1 db gain com pression . in the upper band of 70 ghz to 90 ghz , the adl7003 provides 1 5 db (typical) of gain , 2 1 dbm output ip3, and 1 4 dbm of output power for 1 db gain compression. the adl7003 requires 120 ma from a 3 v supply. the adl7003 amplifier inputs/outputs are internally matched to 50 , facilitating integration into multichip modules (mcms). all data is taken with the chip connected via one 0.0 76 mm ( 3 mil) ribbon b ond of 0.076 mm (3 mil) minimal length .
adl7003 data sheet rev. 0 | page 2 of 18 table of contents features ........................................................................................... 1 applications ................................................................................... 1 functional block diagram ............................................................ 1 general de s cr ip t io n ...................................................................... 1 revision history ............................................................................ 2 specifications ................................................................................. 3 50 ghz to 70 ghz frequency range ....................................... 3 70 ghz to 90 ghz frequency range ....................................... 3 90 ghz to 95 ghz frequency range ....................................... 4 absolute maximum ratings ......................................................... 5 thermal resistance ................................................................... 5 es d ca u t io n ............................................................................... 5 pin configuration and function descriptions ............................ 6 interface schematic ................................................................... 7 typical performance characteristics ............................................ 8 theory of operation .................................................................... 13 applications information ............................................................ 14 mounting and bonding techniques for millimeterwave gaas mmics ..................................................................................... 14 typical application circuit ..................................................... 16 assembly diagram ................................................................... 17 outline dimensions .................................................................... 18 ordering guide ........................................................................ 18 revision histor y 4/2017 revision 0 : initial version
data sheet adl7003 rev. 0 | page 3 of 18 specifications 50 g h z to 70 gh z frequency range t die bottom = 25c; v dd = v dd 1a = v dd 2a = v dd 3a = v dd 4a = 3 v; i dq = i dq 1a + i dq 2a + i dq 3a + i dq 4a = 12 0 ma, unless otherwise noted . adjust v gg = v gg 12a = v gg 34 a from ? 1.5 v to 0 v to achieve the desired i dq . typical v gg = ? 0.5 v for i dq = 120 ma. table 1 . parameter symbol min typ max unit test conditions/ comments frequency range 50 70 ghz gain 14 db gain variation over temperature 0.0 2 db/ c noise figure 5 db return loss input s11 1 5 db output s22 20 db output output power for 1 db compression p1db 1 2 dbm saturated output power p s at 16 dbm output third - order intercept o ip3 21 dbm output power ( p out ) /tone = 0 dbm with 1 mhz tone spacing input input thir d - order intercept iip3 7 dbm p out /tone = 0 dbm with 1 mhz tone spacing supply current i dq 120 180 ma adjust v gg to achieve i dq = 120 ma typical voltage v dd 2 3 4 v 7 0 gh z to 90 gh z frequency range t die bottom = 25c; v dd = v dd 1a = v dd 2a = v d d 3a = v dd 4a = 3 v ; i dq = i dq 1a + i dq 2a + i dq 3a + i dq 4a = 120 ma, unless otherwise note d. adjust v gg = v gg 12a = v gg 34a from ? 1.5 v to 0 v to achieve the desired i dq . typica l v gg = ? 0.5 v for i dq = 120 ma. table 2 . parameter symbol min typ max unit test conditions/ comments frequency range 70 90 ghz gain 13 15 db gain variation over temperature 0.0 2 db/ c noise figure 5.5 6.5 db return loss input s11 15 db output s22 15 db output output power for 1 db compression p1db 1 4 dbm saturated output power p s at 18 dbm output third - order intercept o ip3 21 dbm p out /ton e = 0 dbm with 1 mhz tone spacing input input third - order intercept iip3 6 dbm p out /tone = 0 dbm with 1 mhz tone spacing supply current i dq 120 180 ma adjust v gg to achieve i dq = 120 ma typical voltage v dd 2 3 4 v
adl7003 data sheet rev. 0 | page 4 of 18 9 0 g h z to 95 gh z fr equency range t die bottom = 25c; v dd = v dd 1a = v dd 2a = v dd 3a = v dd 4a = 3 v; i dq = i dq 1a + i dq 2a + i dq 3a + i dq 4a = 120 ma, unless otherwise noted . adjust v gg = v gg 12a = v gg 34a from ? 1.5 v to 0 v to achieve the desired i dq . typical v gg = ? 0.5 v for i dq = 12 0 ma. table 3 . parameter symbol min typ max unit test conditions/ comments frequency range 90 95 ghz gain 11 db gain variation over temperature 0.0 2 db/ c return loss input s11 15 db output s22 15 db sup ply current i dq 120 180 ma adjust v gg to achieve i dq 120 ma typical voltage v dd 2 3 4 v
data sheet adl7003 rev. 0 | page 5 of 18 a bsolute maximum rati ngs table 4 . parameter rating drain bias voltage (v dd ) 4.5 v gate bias voltage (v gg ) ? 2 v to 0 v dc radio frequency (rf) input power (rfin) 15 dbm continuous power dissipation ( p d i ss ) , at t d i e bottom = 85 c ( d erate 15 .00 mw/ c a bove 85 c) 1.350 w storage temperature range (ambient) ? 6 5 c to + 150 c operating temperature range (die botto m ) ? 55 c to +85 c esd sensitivity human body model ( hbm) class 1a 250 v channel temperature to maintain 1 million hour mttf 175 c nominal channel temperature at t d i e bottom = 85 c, v dd = 3 v 110c stresses at or above those listed under absolute maxim um ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type jc unit c - 14 - 5 66.70 c/w esd caution
adl7003 data sheet rev. 0 | page 6 of 18 p in configuratio n and function descr iptions 9 10 11 12 13 14 1 8 7 6 5 4 3 2 adl7003 top view (not to scale) rfin rfout v dd 4a v dd 3a v gg 34a v dd 2a v dd 1a v gg 12a v dd 2b v dd 3b v dd 4b v dd 1b v gg 34b v gg 12b 15691-002 figure 2 . pad configuration table 6 . pad function descriptions pad no. mnemonic description 1 rfin rf input. this p ad is ac - coupled and matched to 50 ?. see figure 3 for the interface schematic. 2 v gg 12a gate control pad for the first and second stage amplifiers. see figure 4 for the interface schematic. 3, 4 v dd 1 a , v dd 2a drain bias voltage pa ds for the first and second stage amplifiers. external bypass capacitors of 1 2 0 pf, 0.1 f, and 4.7 f are required. connect these pads to a 3 v supply. see figure 5 for the interface schematic. 5 v g g 34a gate cont rol pad for the third and fourth stage amplifiers . see figure 4 for the interface schematic. 6 , 7 v d d 3a, v dd 4a drain bias voltage pads for the third and fourth stage amplifiers. external bypass capacitors of 1 2 0 p f, 0.1 f, and 4.7 f are required. connect these pads to a 3 v supply. see figure 5 for the interface schematic. 8 rfout rf output. this pad is ac - coupled and matched to 50 ?. see figure 9 for the interface schematic. 9, 10 v dd 4b, v dd 3b drain bias voltage pads for the fourth and th ird stag e alternative bias configuration. external b ypass capacitors of 1 2 0 pf, 0.1 f, and 4.7 f are required. see figure 7 for the interface schematic. 11 v gg 34b gate control pad for the third and fourth stage alternative bias configuration. coupling capacitors are required. see figure 8 for the interface schematic. 12, 13 v dd 2b, v dd 1b drain bias voltage pads for the second and first stage alternative bias configuration. external bypass capacitors of 1 2 0 pf, 0.1 f, and 4.7 f are required. see figure 7 for the interface schematic. 14 v gg 12b gate control pad for the first and second stage alternative bias configuration. coupling capacitors are required. see figure 8 for the interface schematic. die bottom gnd ground. die bottom must be connected to rf/dc ground. see figure 6 for the interface schematic.
data sheet adl7003 rev. 0 | page 7 of 18 interface schemati c rfin 15691-003 figure 3 . rfin interface schematic v gg 12a, v gg 34a 15691-004 figure 4 . v gg 12a , v gg 34a interface schematic v dd 1a to v dd 4a 15691-005 figure 5 . v dd 1a to v dd 4a interface schematic gnd 15691-006 figure 6 . gnd interface schema tic v dd 1b to v dd 4b 15691-007 figure 7 . v dd 1b to v dd 4b interface schematic v gg 12b, v gg 34b 15691-008 figure 8 . v gg 12b , v gg 34b interface schematic rfout 15691-009 figure 9 . rfout interface schematic
adl7003 data sheet rev. 0 | page 8 of 18 typical performance characteri stics 20 ?30 15 40 100 response (db) frequency (ghz) ?25 ?20 ?15 ?10 ?5 0 5 10 45 50 55 60 65 70 75 80 85 90 95 s11 s21 s22 15691-010 figure 10 . broadband gain and return loss vs. frequency 20 0 50 95 gain (db) frequency (ghz) +85c +25c ?55c 2 4 6 8 10 12 14 16 18 55 60 65 70 75 80 85 90 15691-013 figure 11 . gain vs. frequency for various temperature s 20 0 gain (db) 2 4 6 8 10 12 14 16 18 50 95 frequency (ghz) 55 60 65 70 75 80 85 90 100ma 120ma 140ma 160ma 180ma 15691-020 figure 12 . gain vs. frequency for various i d q val ues 20 0 gain (db) 2 4 6 8 10 12 14 16 18 50 95 90 frequency (ghz) 55 60 65 70 75 80 85 2.0v 2.7v 3.0v 3.3v 4.0v 15691-027 figure 13 . gain vs. frequency for various v dd values 0 ?26 50 95 input return loss (db) frequency (ghz) ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 55 60 65 70 75 80 85 90 +85c +25c ?55c 15691-0 1 1 figure 14 . input return loss vs. frequency at various temperatur e s 0 ?26 input return loss (db) ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 50 95 frequency (ghz) 55 60 65 70 75 80 85 90 100ma 120ma 140ma 160ma 180ma 15691-018 figure 15 . input return loss vs. frequency for various i d q values
data sheet adl7003 rev. 0 | page 9 of 18 0 ?26 50 95 input return loss (db) frequency (ghz) ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 55 60 65 70 75 80 85 90 2.0v 2.7v 3.0v 3.3v 4.0v 15691-028 figure 16 . input return loss vs. frequency for various v dd values 0 ?26 50 95 output return loss (db) frequency (ghz) ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 55 60 65 70 75 80 85 90 +85c +25c ?55c 15691-014 figure 17 . output return loss vs. frequency for various temperatures 50 95 frequency (ghz) 55 60 65 70 75 80 85 90 100ma 120ma 140ma 160ma 180ma 0 ?26 output return loss (db) ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 15691-021 figure 18 . output return loss vs. frequency for various i d q values 0 ?26 output return loss (db) ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 50 95 frequency (ghz) 55 60 65 70 75 80 85 90 2.0v 2.7v 3.0v 3.3v 4.0v 15691-031 figure 19 . output return loss vs. frequency for various v dd values 10 0 noise figure (db) 50 90 frequency (ghz) 55 60 65 70 75 80 85 +85c +25c ?55c 1 2 3 4 5 6 7 8 9 15691-012 figure 20 . noise figure vs. frequency at various temperatures 8 0 2 5 7 4 1 3 6 noise figure (db) 100ma 120ma 140ma 160ma 180ma 50 90 frequency (ghz) 55 60 65 70 75 80 85 15691-022 fi gure 21 . noise figure vs. frequency for various i d q values
adl7003 data sheet rev. 0 | page 10 of 18 50 90 frequency (ghz) 10 0 noise figure (db) 1 2 3 4 5 6 7 8 9 55 60 65 70 75 80 85 2.0v 2.7v 3.0v 3.3v 4.0v 15691-029 figure 22 . noise figure vs. frequency for various v dd values 20 0 50 90 output p1db (db) frequency (ghz) 2 4 6 8 10 12 14 16 18 55 60 65 70 75 80 85 +85c +25c ?55c 15691-015 figure 23 . output p1db vs. frequency at various tem perature s 20 0 p1db (dbm) 100ma 120ma 140ma 160ma 180ma 2 4 6 8 10 12 14 16 18 50 90 frequency (ghz) 55 60 65 70 75 80 85 15691-025 figure 24 . p1db vs. frequency for various i d q values 50 90 frequency (ghz) 20 0 p1db (dbm) 55 60 65 70 75 80 85 2.0v 2.7v 3.0v 3.3v 4.0v 2 4 6 8 10 12 14 16 18 15691-032 figure 25 . p1db vs. frequency for various v dd values 20 0 p sat (dbm) 2 4 6 8 10 12 14 16 18 +85c +25c ?55c 50 90 frequency (ghz) 55 60 65 70 75 80 85 15691-016 figure 26 . p sat vs. frequency at various temperatu re s 50 95 20 0 p sat (dbm) frequency (ghz) 2 4 6 8 10 12 14 16 18 100ma 120ma 140ma 160ma 180ma 55 60 65 70 75 80 85 90 15691-023 figure 27 . p sat vs. frequency at various i d q values
data sheet adl7003 rev. 0 | page 11 of 18 50 90 frequency (ghz) 20 0 p sat (dbm) 55 60 65 70 75 80 85 2.0v 2.7v 3.0v 3.3v 4.0v 2 4 6 8 10 12 14 16 18 15691-030 figure 28 . p sat vs. frequency for various v dd values 12 11 10 9 8 7 6 5 4 3 2 1 0 input ip3 (db) 50 55 90 frequency (ghz) 60 65 70 75 80 85 +85c +25c ?55c 15691-019 figure 29 . iip3 vs. frequency at various temperature s 12 11 10 9 8 7 6 5 4 3 2 1 0 input ip3 (dbm) 50 90 frequency (ghz) 55 60 65 70 75 80 85 100ma 120ma 140ma 160ma 180ma 15691-024 figure 30 . iip3 vs. frequency for various i d q values 12 11 10 9 8 7 6 5 4 3 2 1 0 50 90 55 60 65 70 75 80 85 input ip3 (dbm) frequency (ghz) 2.0v 2.7v 3.0v 3.3v 4.0v 15691-033 figure 31 . iip3 vs. frequency for various v dd values 26 10 output ip3 (db) 50 90 frequency (ghz) 55 60 65 70 75 80 88 +85c +25c ?55c 12 14 16 18 20 22 24 15691-017 figure 32 . oip3 vs. frequency at various temperature s 26 10 50 90 output ip3 (dbm) frequency (ghz) 12 14 16 18 20 22 24 55 60 65 70 75 80 85 100ma 120ma 140ma 160ma 180ma 15691-026 figu re 33 . oip3 vs. frequency for various i d q values
adl7003 data sheet rev. 0 | page 12 of 18 26 10 output ip3 (dbm) 12 14 16 18 20 22 24 50 90 frequency (ghz) 55 60 65 70 75 80 85 2.0v 2.7v 3.0v 3.3v 4.0v 15691-034 figure 34 . oip3 vs. frequency for various v dd values 0.30 0.25 0.20 0.15 0.10 0.05 ?0.10 ?0.05 0 ?15 15 gate supply current (ma) rf input power (dbm) ?12 ?9 ?6 ?3 0 3 6 12 9 70ghz 75ghz 80ghz 85ghz 15691-035 figure 35 . gate supply current (i dd ) vs. rf input power 300 100 120 140 160 180 200 220 240 260 280 drain supply current (ma) ?15 15 rf input power (dbm) ?12 ?9 ?6 ?3 0 3 6 9 12 70ghz 75ghz 80ghz 85ghz 15691-036 figure 36 . drain supply current (i dd ) vs. rf input power 450 400 350 300 250 200 150 100 50 0 drain supply current (ma) ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 gate supply voltage (v) 2.0v 2.7v 3.0v 3.3v 4.0v 15691-050 figure 37 . drain supply current (i d q ) vs. gate supply voltage (v gg )
data sheet adl7003 rev. 0 | page 13 of 18 theory of operation the architecture of the adl7003 low noise amplifier is shown in figure 38 . the adl7003 uses two cascaded four - stage amplifiers operating in quadra ture between two 90 hybrids. this balanced amplifier approach forms an amplifier with a combined gain of 1 4 db and a saturated output power (p sat ) of 1 8 dbm . the 90 hybrids ensure that the input and output return losses are greater than or equal to 15 db . see the application circuit shown in figure 41 for further details on biasing the various blocks. rfin rfout 15691-037 figure 38 . adl7003 ar chitecture
adl7003 data sheet rev. 0 | page 14 of 18 applications informa tio n the adl7003 is a gaas, phemt, mmic power amplifier. capacitive bypassing is required for v dd 1a through v dd 4a and v dd 1b through v dd 4b (see figure 41 ) . v gg 12a is the gate bias pad for the first two gain stages. v gg 34a is the gate bias pad for the second two gain stages. apply a gate bias voltage to v gg 1 2a an d v gg 34a , and use capacitive bypassing as shown in figure 41 . all measurements for this device were taken using the typical application circuit ( see figure 41 ) and configured as shown in the assembly diagram ( figure 42 ) . the following is the recommended bias sequence during power - up: 1. connect to ground. 2. set the gate bias voltage to ? 1.5 v . 3. set all the drain bias voltages, v dd = 3 v. 4. increase the gate bias voltage to achieve a quiescent current, i dd = 120 ma. 5. apply the rf signal. the following is the recommended bias sequence during power - down: 1. turn off the rf signal. 2. decrease the gate bias voltage to ? 1.5 v to achieve i dd = 0 ma (approximately). 3. decrease all of the drain bias voltages to 0 v. 4. incr ease the gate bias voltage to 0 v. table 7 . power select ion table 1 i d q (ma) 2 gain (db) p1db (dbm) oip3 (dbm) p diss (mw) v gg (v) 100 12 10 20 300 ? 0.52 120 13 12 21 360 ? 0.49 140 14 13 22 420 ? 0.44 160 15 14 22.5 480 ? 0.40 180 1 6 15 23 540 ? 0.36 1 data taken at nominal bias conditions; v dd = 3 v, t a = 25c . 2 adjust v gg 12a and v gg 24a from ?1.5 v to 0 v to ac hieve the desired drain current . the vdd = 3 v and idd = 12 0 ma bias conditions are recom - mended to optimize overall perfo rmance. unless otherwise noted, the data shown was taken using the recommended bias condition. operation of the adl7003 at different bias conditions may provide performance that differs from wh at is shown in figure 41 . biasing the adl7003 for higher drain current typically results in higher p1db, output ip3, and gain but at the expense of inc reased power consumption (see ta b le 7 ). mounting and bonding techniques for millimeterwave g a a s mmic s attach the die directly to the ground plane with conductive epoxy (see the handling pr ecautions section, the m ounting section, and the wire bonding section). microstrip, 50 ? transmission lines on 0.127 mm (5 mil) thick alumina, thin film substrates are recommended for bringing the radio frequency to and from the chip. raise the die 0.075 mm (3 mil) to ensure that the surface of the die is coplanar with the sur face of the substrate. place microstrip substrates as close to the die as possible to minimize ribbon bond length. typical die to substrate spacing is 0.076 mm to 0.152 mm (3 mil to 6 mil). to ensure wideband matching , a 15ff capacitive stub is recommended on the pcb board before the ribbon bond. l9301 mmic pcb board 50 transmission line m a tching stub/bond p ad shunt ca p aci t ance = 15ff 3mil gold ribbon 3mil gap 15691-051 rfin figure 39 . high frequency input wideband matching 15691-052 l9301 mmic pcb board 50 transmission line m a tching stub/bond p ad shunt ca p aci t ance = 15ff 3mil gap rfout 3mil gold ribbon figure 40 . high frequency output wideband matching place microstrip substrates as close to the die as possib le to minimize bond wire length. typical die to substrate spacing is 0.076 mm to 0.152 mm (3 mil to 6 mil).
data sheet adl7003 rev. 0 | page 15 of 18 handling precautions to avoid permanent damage, follow these storage, cleanliness, static sensitivity, transient, and general handling precautions : ? place all bare die in either waffle or gel - based esd protective containers and then seal the die in an esd protective bag for shipment. after the sealed esd protective bag is opened, store all die in a dry nitrogen environment. ? handle the chips in a clea n environment. do not attempt to clean the chip using liquid cleaning systems. ? follow esd precautions to protect against esd strikes. ? while bias is applied, suppress instrument and bias supply transients. use shielded signal and bias cables to minimize ind uctive pickup. ? handle the chip along the edges with a vacuum collet or with a sharp pair of bent tweezers. the surface of the chip may have fragile air bridges and must not be touched with vacuum collet, tweezers, or fingers. mounting bef or e epoxy die is attached, apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip after it is placed into position. cure the epoxy per the schedule of the manufacturer. wire bonding rf bonds made with 0.003 in. 0.0005 in. gold ribbon are recommended for the rf ports. these bonds must be thermo - sonically bonded with a force of 40 g to 60 g. dc bonds of 0.001 in. (0.025 mm) diameter, thermosonically bonded, are recommended. create ball b onds with a force of 40 g to 50 g and we dge bonds with a force of 18 g to 22 g. create all bonds with a nominal stage temperature of 150c. apply a minimum amount of ultrasonic energy to achieve reliable bonds. keep all bonds as short as possible, less tha n 12 mil (0.31 mm). alternatively, short ( 3 mil) rf bonds made with two 1 - mil wires can be used.
data sheet adl7003 rev. 0 | page 16 of 18 typical application circuit the drain and gate voltages can be applied to either the north or the south side of the circuit. 15691-053 nc nc rfin rfout v dd 2b v dd 3b v dd 4b v dd 1b v gg 34b v gg 12b rfin rfout adl7003 v dd 4a v dd 3a v gg 34a v dd 2a v dd 1a v gg 12a 120pf 0.1f 4.7f 120pf 120pf 120pf 120pf 120pf 120pf 120pf 120pf 120pf 120pf 120pf 0.1f 0.1f 0.1f 4.7f 4.7f 4.7f v dd 1a to v dd 4 a v gg 12a to v gg 34a no dc bias applied 9 10 11 12 13 14 1 8 7 6 54 3 2 figure 41. typical application circuit
data sheet adl7003 rev. 0 | page 17 of 18 assembly diagram 15691-055 figure 42 . assembly diagram
adl7003 data sheet rev. 0 | page 18 of 18 outline dimensions 04-26-2017- a 1.90 sq 0.05 side view 1 8 0.207 0.208 0.117 2 3 4 5 6 7 9 10 1 1 12 13 14 0.201 0.150 0.150 0.150 0.150 0.150 0.150 0.150 0.150 0.150 0.150 0.088 0.088 0.637 0.125 0.125 1.016 0.125 0.125 * airbridge are a * this die utilizes fragile air bridges. any pickup tools used must not contact this area. 0.076 0.076 (pads 2-7, 9-14) 0.086 0.051 (pads 1 & 8) 0.081 0.097 figure 43 . 14 - pad bare die [chip] (c - 14 - 5) dimensions shown in millimeter ordering guide model temperature range package description package option adl7003 chips ?55c to +85c 1 4 - pad bare die [chip] c - 1 4 - 5 adl7003chips - sx ?55c to +85c 1 4 - pad bare die [chip] c - 1 4 - 5 ? 2017 analog devices, i nc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d15691 - 0- 4/17(0)

▲Up To Search▲

Price & Availability of ADL7003CHIPS-SX

	To Download ADL7003CHIPS-SX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .